Algoritmi | User | Rui Pedro Oliveira Machado
Rui Pedro Oliveira Machado
Rui Pedro Oliveira Machado
At LASI
Other with MSc
Member of the CALG R&D Unit
Academic Degree
MSc
Current Position
Other at Escola de Engenharia da Universidade do Minho
Personal Webpage
Personal Email
a58778@alunos.uminho.ptOrcid
0000-0001-9929-8705Researcher ID
A-4877-2016FCT Public Key
J652359f16cr
Ciência ID
6,86E+15Google Scholar
Publications (11)
Efficient Hardware Design and Implementation of the Voting Scheme-Based Convolution
Sensors
2022 | journal-article
Customizable FPGA-Based Hardware Accelerator for Standard Convolution Processes Empowered with Quantization Applied to LiDAR Data
Sensors
2022 | journal-article
Gray-Code TDC with Improved Linearity and Scalability for LiDAR applications
2020 6th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)
2020 | conference-paper
Technology Independent ASIC Based Time to Digital Converter
IEEE Access
2020 | journal-article
All-Digital Time-to-Digital Converter Design Methodology Based on Structured Data Paths
IEEE Access
2019 | journal-article
Designing Synchronizers for Nutt-TDCs
Proceedings - 5th International Conference on Event-Based Control, Communication and Signal Processing, EBCCSP 2019
2019 | conference-paper
Recent Developments and Challenges in FPGA-Based Time-To-Digital Converters
IEEE Transactions on Instrumentation and Measurement
2019 | journal-article
A novel synchronizer for a 17.9ps Nutt Time-to-Digital Converter implemented on FPGA
2018 110th AEIT International Annual Conference, AEIT 2018
2018 | conference-paper
FPGA vendor-agnostic IP-XACT- and XSLT-based RTL design generator
2016 18th Mediterranean Electrotechnical Conference (MELECON)
2016 | conference-paper
Hardware-assisted Real-Time Operating System Deployed on FPGA
VDI Verlag
2014 | book-chapter
Hardware-assisted Real-Time Operating System Deployed on FPGA
Fortschritt-Berichte Vdi
2014 | book-chapter
Efficient Hardware Design and Implementation of the Voting Scheme-Based Convolution
Sensors
2022 | journal-article
Customizable FPGA-Based Hardware Accelerator for Standard Convolution Processes Empowered with Quantization Applied to LiDAR Data
Sensors
2022 | journal-article
Gray-Code TDC with Improved Linearity and Scalability for LiDAR applications
2020 6th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)
2020 | conference-paper
Technology Independent ASIC Based Time to Digital Converter
IEEE Access
2020 | journal-article
All-Digital Time-to-Digital Converter Design Methodology Based on Structured Data Paths
IEEE Access
2019 | journal-article
Designing Synchronizers for Nutt-TDCs
Proceedings - 5th International Conference on Event-Based Control, Communication and Signal Processing, EBCCSP 2019
2019 | conference-paper
Recent Developments and Challenges in FPGA-Based Time-To-Digital Converters
IEEE Transactions on Instrumentation and Measurement
2019 | journal-article
A novel synchronizer for a 17.9ps Nutt Time-to-Digital Converter implemented on FPGA
2018 110th AEIT International Annual Conference, AEIT 2018
2018 | conference-paper
FPGA vendor-agnostic IP-XACT- and XSLT-based RTL design generator
2016 18th Mediterranean Electrotechnical Conference (MELECON)
2016 | conference-paper
Hardware-assisted Real-Time Operating System Deployed on FPGA
VDI Verlag
2014 | book-chapter
Hardware-assisted Real-Time Operating System Deployed on FPGA
Fortschritt-Berichte Vdi
2014 | book-chapter
